A nonvolatile memory module may include multiple nonvolatile memory rows and can be partitioned to odd and even nonvolatile memory pages. An odd nonvolatile memory page may include odd row portions. An even nonvolatile memory page may include even row portions. A pair of consecutive nonvolatile memory pages (one even and one odd) may include odd and even portions of the same rows.
Programming may be performed by programming an even nonvolatile memory page that may include even row portions of certain rows, and programming an odd nonvolatile memory page that may include odd row portions of these certain rows.
FIG. 1 illustrates a prior art writing scheme for nonvolatile memory module 199. The memory module may include sixty-four nonvolatile memory pages 100-163. Nonvolatile memory module 199 may include thirty-two odd nonvolatile memory pages 101, 103, 105, . . . 163, and thirty-two even nonvolatile memory pages 102, 104, 106, . . . 162. Each pair of consecutive nonvolatile memory pages (e.g., 100 and 101, 102 and 103, 104 and 105, . . . 162 and 163) may include row portions of the same rows.
With reference to FIG. 1, first codeword portion CW0a of codeword CW0 may be programmed to the first even nonvolatile memory page. A second codeword portion CW0b of CW0 may be programmed to the first odd nonvolatile memory page, where both the first even and first odd nonvolatile memory pages may include portions of the same rows. To generalize, first codeword portion CWKa of codeword CWK may be programmed to the (K+1) even nonvolatile memory page. A second codeword portion CWKb of codeword CWK may be programmed to the (K+1) odd nonvolatile memory page.
FIG. 2 depicts a graph showing differences in voltage threshold lobes for a 2-bit per cell memory device in accordance with the prior art writing scheme of FIG. 1. FIG. 2 illustrates that after a retention test, which may simulate the behavior of a flash memory module after a period of time, the average locations of threshold voltage lobes vary between nonvolatile memory pages. Before the retention test the average lobe threshold voltage was about equal for all nonvolatile memory pages. FIG. 2 depicts the average lobe location [V] as function of the page index, where curve 0 refers to the erase lobe, curve 1 refers to the first (lowest) non-zero lobe, and curve 4 refers to the highest voltage lobe. As may be noticed from FIG. 2, some pages suffer a large average shift due to retention, while on other pages the average shift is smaller.
FIG. 3 depicts a graph showing the number of errors, after retention testing, in accordance with the prior art writing scheme of FIG. 1. The graph depicts the number of errors, after retention testing, as a function of the nonvolatile memory page index under the prior art writing scheme of FIG. 1 for least significant bit (LSB) nonvolatile memory pages of a 2-bit per cell non-volatile memory module, where the read operation is done using the optimal read thresholds per page. It may be noticed that in accordance with FIG. 2, which exemplified a variable lobe shift per page, the number of errors increases with the page index.